In the ongoing search for higher levels of circuit integration to support system level requirements, many avenues have been explored. In particular, chip feature sizes have been substantially reduced; wafer processing technologies have been altered to allow different types of circuits on the same chip; and package sizes and foot prints have been minimized. Each approach is limited by state-of-the-art technology and cost constraints, both from the device manufacturer and the end user.
An approach for integration of functions and reduction of device size which facilitates more compact, higher performance systems is the assembly of multiple chips in a single package. Multiple chips of the same or of different device technologies are included on an interconnecting substrate and/or in a single package which provides contacts to the next level of interconnection.
Integration of multiple chips in the same package has been developed both in the horizontal and vertical planes. Historically, the vertical integration of memory circuits has provided a stacked device 10 having an increased memory capacity within the same footprint as a single device, as shown in FIG. 1. A number of similar chips 11 of relatively low pin count are connected to individual interposers 13. The assemblies are stacked atop each other, and interconnected to each other, and to external contacts 12.
More recently, as shown in FIG. 2, multiple silicon chips 21 of different types have been assembled in a vertical stack with standoffs 24 between each of the active devices 21 to separate and allow interconnections to be made to substrate 23. Chips 21 are interconnected by conductive traces on substrate 23. Typically each chip 21 is separated from the vertically successive chip by an insulating material 24. A stacked chip assembly is of particular importance for coupling an integrated circuit to a memory device, such as a random access memory, E2prom, flash memory or buffer storage, where rapid interaction between chips is crucial. Wafer fabrication of memory circuits is not readily compatible with other IC wafer fabrication technologies, and is difficult and costly to integrate. Therefore, the assembly of stacked chips for providing a rapid interaction with functional chips is cost effective.
Materials which have been used as stand-offs to separate the vertically stacked chips include polymeric films, laminate materials, adhesives, bare silicon chips, and/or a combination of such materials.
Polymeric films may be applied to the wafer and photo patterned to expose the bonding pads, thereby offering the advantage of processing as wafers with multiple chips, rather than as individual chips during final assembly of the devices. However, each additional processing step adds significantly to the wafer cost and increases the probability of introducing defects which contribute to costly yield losses. Other types of materials used as standoffs most frequently require insertion into individual packages during assembly.
Wire bonding is a widely used method to connect each semiconductor chip to the substrate or package. The bond pad is an electrically conductive metal area on the surface of the IC where bonding wires, typically of gold are connected. Copper has become commonly used for some interconnects 311 in integrated circuits, replacing aluminum. However, because of problems bonding to copper, bond pads 31 for chips with copper interconnection technology often utilize an aluminum layer 33 to cap the exposed copper bond pads 31 as illustrated in a cross-sectional view of a portion of a chip 30 in FIG. 3. The aluminum cap 33 covers the copper pad 31 and overlaps onto the passivation layer 32, thereby allowing use of the same wire bonding tools and processes as those used for chips having aluminum interconnect technologies.
It is well known that as the size of brittle silicon chips has increased, and the chips are adhered to substrates of different materials, thermal and mechanical stresses develop which can result in yield and reliability failures. Not only can the stresses be of a concern for mechanical distortion and cracking of the chips, interconnections, or interconnection interfaces, but in high speed devices, response times of the chip may be altered, thereby interfering with device performance. Avoiding inclusion of thick, continuous layers of materials having dissimilar coefficients of expansion helps to mitigate thermally induced stresses on the silicon chips.
Another major concern for vertically stacked chips is yield loss due to defects induced either during added processing steps which are necessary to prepare the chips for assembly or during the assembly process itself. Additional processing steps are costly because of fabrication expenses and yield losses.
A method for reliable, high density assembly of semiconductor chips within a small foot print is an important goal; and a method for cost effective assembly of such devices, wherein existing technologies and equipment are utilized, would be welcome.